Digital Control Systems 1.02

In the previous blog we introduced the various types of signals present in a digital control system and highlighted the pros and cons. In this blog we take a a closer look at the digital control system.

A digital control system, can only cope with digital signals. That is because it is inherently discrete in time and space. This is caused by the processors clock rate and due to the finite word length of a digital system. For instance, a 32 [bit] computer which runs at 4 [GHz] has a time resolution of 0.25 [ns] and the value of an unsigned integer can only range from 0 to 232 − 1.

Figure 1. Digital control system in its most elementary form. Continuous-time signals are in solid and discrete-time signals are dashed.

Figure 1 shows the digital control system in its most elementary form. Herein \mathcal{S} is the sampler. The sampler converts the analog output signal of the plant y(t) at time t \in \mathbb{R} to a digital measurement signal y[k] at discrete-time k \in \mathbb{N}. As mentioned in the previous blog, the digital signal is obtained by sampling and quantization of the analog signal. In final, \mathcal{H} denotes the recronstructor, also known as a digital-analog convertor (DAC), it converts the digital control signal u[k] provided by the controller to an analog control signal u(t).


Figure 2 shows that the sampler exists out of two devices namely; i) a sample and hold (SH) device and ii) a analog-digtal convertor (ADC).

Figure 2. The sampler and its sub systems.

The SH device knows two different states. The first state is called the track state at which the analog input signal is tracked by the SH device. The track state is also refereed to as sample state. However because of the ambiguous meaning of the word sample we will use the track, which is also commonly used in literature. The second state is called the hold state at which the analog input signal is being kept constant for a short period of time. The hold state is activated when the hold command is given. During the hold state the ADC is able to process and digitize the signal. The hold command can be triggered by any logic device. While there are many more aspects and subtleties to be considered with a SH device this gives a summarized overview of its functionality.

Figure 3. The track and hold of a SH. Dashed red shows the original signal, solid blue shows the SH signal.

Various different strategies exists at what time instance t_k the hold command is triggered. These are called sampling strategies.

  1. Periodic sampling; the sampling instances t_k are equally spaced, that is to say t_k = kh with k \in \mathbb{N} and h, given in [s], being the sampling period. See also Figure 2(a). The sampling period h is often also denoted as the sampling rate or sampling frequency f_s, given in [Hz]. It is related to the sampling period by h = \frac{1}{f_s}.
  2. Multi-order sampling; a pattern of sampling instances \{t_k\} are repeated periodically, as a result t_{k+r} = t_k. See Figure 2(b).
  3. Event-based sampling; the sampling instances t_k are generated based on a event in the system. For instance, when a certain measurement threshold has been crossed. See Figure 2(c) in which the signal is sampled at every \pm0.4x \pm 0.2 value.
  4. Random sampling; the sampling time instances t_k are chosen at random, see Figure 2(d).
Figure 2. Visualization of different sampling techniques. Red line resembles the original analog signal, blue the sampled signal. Matlab code.

Periodic sampling is the most common in industry. That is because of several reason; i) most deterministic behavior, ii) extensively been researched, iii) easiest to model and iv) easiest to obtain key performance indicators, for instance, in time- and frequency domain. Finally, proofing stability for the other sampling strategies is much harder then for periodic sampling.

In the next blog, we will go deeper in the mathematics behind sampling.